This invention relates generally to ferroelectric memory circuits, and, more particularly, to a fabrication technique for patterning, etching, and forming a ferroelectric capacitor stack.
Standard Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) devices are considered volatile memory devices because data stored therein is lost when power is lost. Nonvolatile memory devices are those that can retain data despite loss of power.
At present, there is a strong market for EEPROM (Electrically Erasable, Programmable Read Only Memory), and Flash EEPROM nonvolatile memory devices. These devices tend to be slow to write, often having write times on the order of milliseconds, while read times range generally between one nanosecond and one microsecond. The great difference between read and write times, together with the block-erase character of Flash EEPROM, complicates design of some systems. CMOS SRAM or DRAM with battery backup power for data retention can provide symmetrical, fast, read and write times in nonvolatile memory but is expensive, requires presence of a battery, and limits system life or requires eventual battery replacement.
It is known that Ferroelectric Random Access Memory (FRAM) is a nonvolatile memory technology having potential for both read and write times below one microsecond. FRAM nonvolatile memory devices based on Lead Zirconium Titanate (PZT) ferroelectric storage capacitors as memory elements integrated with CMOS addressing, selection, and control logic are known in the art and are commercially available. PLZT is a Lanthanum-doped form of PZT wherein some of the lead is replaced with Lanthanum, for purposes of this patent the term PZT includes PLZT. It is known that PZT may additionally be doped with strontium and calcium to improve its ferroelectric dielectric properties. Ferroelectric storage capacitors having a Strontium Bismuth Tantalate (SBT) dielectric are also known in the art. For purposes of this patent the term Ferroelectric Dielectric includes both PZT and SBT materials.
It is expected that FRAM devices having smaller device geometries and smaller ferroelectric storage capacitors than currently available devices will offer greater speed and storage density at lower cost. Producing such FRAM devices requires production of well-defined, uniform, high quality, ferroelectric storage capacitors integrated with CMOS addressing and control logic.
Ferroelectric storage capacitors of FRAM devices have a bottom electrode interfacing with a ferroelectric layer, often PZT or SBT, which serves as the ferroelectric dielectric. The ferroelectric layer is typically deposited on top of the bottom electrode, and a top electrode is deposited on top of the ferroelectric layer. These layers are masked and etched to define the size and location of each capacitor. A passivation layer is formed over the resulting capacitors. This layer is masked and etched to allow connection of each capacitor to other components of each memory cell and to other components, such as CMOS addressing, selection, and control logic of the integrated circuit.
A prior process for fabricating an array of ferroelectric storage capacitors is described in U.S. Pat. No. 6,090,443, (the ""443 patent) entitled xe2x80x9cMulti-Layer approach for optimizing Ferroelectric Film Performancexe2x80x9d and assigned to Ramtron International Corporation, Colorado Springs, Colo., the disclosure of which is incorporated herein by reference. This process involves the following steps all performed after deposition of an adhesion layer onto a substrate, the substrate may be a partially processed CMOS integrated circuit wafer:
deposition of a metallic bottom electrode layer;
deposition of a PZT layer;
annealing the deposited PZT; and
depositing a top electrode layer.
Once these layers are deposited, they must be patterned to form an array through at least one masking and etching sequence. Each masking and etching sequence requires deposition of a photoresist over the array of partially processed capacitors, aligning the array with a photomask, exposing, developing, and curing the photoresist, and etching to remove undesired portions of the layers. The etching is controlled by remaining cured photoresist. Etching is typically performed with dry etch techniques, such as plasma etching or ion milling.
It is known that typical dry etch techniques as commonly used in processing capacitor arrays cause damage to the cured photoresist used to control etching. This damage may result in undercutting at edges of resist opening. As cured photoresist layers are eaten away, this damage may also result in undesired etching of those portions of the layers that should remain to form the array.
Typically, fabricating such a capacitor array is performed through a sequence of two or more masking and etching sequences because excessive damage to the photoresist occurs before the undesired portions of the layers are adequately removed. It is known, however, that repeated masking and etching sequences are expensive and can result in undesirable edge profiles of remaining portions as a result of misalignment. The undesirable edge profiles may necessitate greater spacing between capacitor array elements than may be otherwise possible. In particular, it is repeated photomasking operations that drive up cost.
It is also known that exposure of photoresist to dry etch causes release of an assortment of chemical compounds that contain carbon and hydrogen. It is also known that excessive exposure of ferroelectric dielectrics, such as PZT, to these compounds, including hydrogen, can induce undesirable properties in the dielectrics. For this patent, induction of undesirable properties by these compounds is known as photoresist byproduct poisoning of the dielectric. It is therefore desirable to protect the dielectric layer from these chemical compounds during the etching process.
A hardmask is a layer of resistant material that is patterned with photolithographic techniques as known in the art and used to control circuit processing. The resistant material is a material that is more stable than cured photoresist under at least some conditions, these conditions may include etching, diffusing, or oxidizing conditions. Hardmask layers are occasionally used in the processing of integrated circuits; although they are typically formed of nonconductive material. For example, standard CMOS processing uses a nonconductive silicon nitride hardmask layer to protect future diffused areas during field oxidation. U.S. Pat. No. 5,936,306 describes a process utilizing a Titanium Silicide layer as a conductive hard mask for controlling wet etch of titanium nitride. U.S. Pat. No. 5,998,258 discloses a process for forming capacitors having a Barium Strontium Titanate dielectric wherein a hardmask layer of Titanium or Tantalum Nitride is used to pattern a top electrode. Pat. No. 5,998,258 also suggests, in column 4, using a hardmask layer in fabrication of capacitors having PZT ferroelectric dielectric and metallic top electrode.
Further processing details related to the use of hardmasks in ferroelectric memory device processing can be founding in co-pending patent RAM 479, Ser. No. 091797,394.
What is desired, therefore, is a technique for easily patterning, etching, and forming a ferroelectric capacitor stack in a ferroelectric memory that is highly manufacturable and minimizes damage to the ferroelectric dielectric layer of the capacitor stack.
It is, therefore, a principal object of the invention to provide a fabrication technique for an integrated circuit ferroelectric memory that is both manufacturable, minimizes the number of processing steps, and also minimizes damage to the ferroelectric dielectric layer.
It is an advantage of the present invention that the temporary PZT encapsulation layer prevents capacitor PZT from losing PbO, thus enhancing ferroelectric capacitor performance.
It is another advantage of the present invention that whereas prior art FRAM integration processes require as many as six photo, etch, and photo resist stripping steps for top electrode and capacitor PZT, the process of the present invention is greatly simplified and requires only one photolithographic and one etching step for patterning both the top electrode and capacitor PZT layers.
It is another advantage of the present invention that it reduces the usage of photolithographic resist material, which undesirably generates hydrogen during etching that can degrade capacitor performance.
It is another advantage of the present invention that it eliminates the photolithographic resist residue stripping process found in prior art processes, thus further reducing the integration damage to PZT capacitors.
It is another advantage of the present invention that it prevents the undesirable formation of xe2x80x9cfencesxe2x80x9d, or the redeposition of etched materials on sidewalls, that are present in prior art processes.
It is another advantage of the process of the present invention that it can be applied to both the capacitor-on-oxide and capacitor-on-plug devices.
It is a feature of the present invention that the temporary PZT encapsulation layer not only provides a partial barrier to lead out-diffusion (a key consideration in ferroelectric capacitor processing), but is in fact a lead source.
It is another feature of the present invention that the deposition of the PZT encapsulation layer is xe2x80x98ferroelectric friendlyxe2x80x99, causing no damage to the underlying ferroelectric capacitor stack, whereas prior art oxide deposition causes severe hydrogen damage to the ferroelectric capacitor that must be annealed out.
It is another feature of the present invention that the temporary PZT encapsulation layer acts as a hydrogen barrier, thus protecting the underlying ferroelectric capacitor during subsequent processing steps, whereas prior art oxide layers provide no such hydrogen protection.
According to the present invention a method of patterning and etching an integrated circuit ferroelectric capacitor uses a layer of PZT that has the same composition as the capacitor PZT as a temporary encapsulation during PZT grain growth annealing. The capacitor PZT is the PZT dielectric layer between the bottom electrode (BE) and the top electrode (TE). The temporary encapsulation PZT also serves as a hard mask to pattern the top electrode and the capacitor PZT layers for a capacitor-on-oxide structure, i.e., two-layer-one-step patterning. The process of the present invention can also be modified for three-layer-one-step patterning for use in a capacitor-on-plug structure.
After the top electrode layer is deposited on a low temperature annealed capacitor PZT layer, a temporary encapsulation layer of PZT that has the same composition as the capacitor PZT is deposited on top surface of the TE. Then the encapsulation PZT is annealed. This anneal also promotes capacitor PZT grain growth. During the anneal, the encapsulation PZT provides lead oxide (PbO) for the capacitor PZT and prevents the capacitor PZT from losing PbO. This process enhances the ferroelectric performance of the capacitor. For the capacitor-on-oxide structure, the TE and capacitor PZT layers are then patterned by one photolithograph/etch step using the temporary encapsulation PZT layer as a hard mask. This patterning process is designated as xe2x80x9ctwo-layer-one-step patterningxe2x80x9d. For a capacitor-on-plug structure, the TE, capacitor PZT, and BE can be patterned by one photolithograph/etch step due to the temporary encapsulation PZT layer as a hard mask. This is referred to as xe2x80x9cthree-layer-one-step patterningxe2x80x9d. Based on the etch rates of photo resist, PZT, TE, and BE, the thickness of encapsulation PZT and photo resist material is selected so that the encapsulation PZT is nearly completely removed when the TE/PZT or TE/PZT/BE etch is completed. Since the photo resist is completely removed during etching, a prior art photo resist residual stripping process is eliminated.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings.